Sic power device having a high voltage termination

ABSTRACT

In one general aspect, an apparatus can include a semiconductor region including a silicon carbide material and a junction termination extension implant region disposed in the semiconductor region. The apparatus can include a low interface state density portion of a dielectric layer having at least a portion in contact with the junction termination extension implant region.

RELATED APPLICATION

This application claims priority to and the benefit of U.S. ProvisionalApplication No. 62/036,925, filed Aug. 13, 2014, entitled, “SIC POWERDEVICE HAVING A HIGH VOLTAGE TERMINATION,” which is incorporated hereinby reference in its entirety.

TECHNICAL FIELD

This description relates to a silicon carbide (SiC) power device havinga high voltage termination.

BACKGROUND

Known high voltage power devices in silicon carbide (SiC) are vulnerableto premature breakdown around a device periphery. The breakdown voltageat device periphery can be lower than the avalanche breakdown voltage inthe bulk of the device. Known solutions for termination regions do notprovide sufficient process stability or can consume relatively largechip areas. Known solutions for termination of high voltage SiC powerdevice do not yield uniform avalanche breakdown in the bulk of SiC.Also, known solutions for high voltage termination of power devices donot eliminate early breakdown at device periphery.

SUMMARY

In one general aspect, an apparatus can include a semiconductor regionincluding a silicon carbide material and a junction terminationextension implant region disposed in the semiconductor region. Theapparatus can include a low interface state density portion of adielectric layer having at least a portion in contact with the junctiontermination extension implant region.

The details of one or more implementations are set forth in theaccompanying drawings and the description below. Other features will beapparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram that illustrates a side cross-sectional view of asilicon carbide (SiC) power device.

FIG. 2 is a diagram that illustrates a variation of the SiC power deviceshown in FIG. 1.

FIG. 3 illustrates a photo micrograph light emission of a SiC PN diode.

FIG. 4 illustrates a sustained Unclamped Inductive Switching (UIS)energy as a function of pulse length.

FIG. 5 is a graph that illustrates a distribution of breakdown voltages.

FIG. 6 illustrates a probe pattern associated with the graph in FIG. 5.

FIG. 7A through 7D illustrate top view images of a test PN diode with amesh electrode.

FIG. 8 is a graph that illustrates breakdown voltage based on zoneratios.

FIG. 9 is a diagram that illustrates formation of a high voltagetermination within a SiC power device.

FIG. 10A is a diagram that illustrates one possible theory associatedwith the devices described herein.

FIG. 10B is a diagram that illustrates a capacitance-voltagecharacteristic of a structure formed using a low interface state densitydielectric.

FIGS. 11A and 11B are additional schematic cross-sections of structuresof SiC power devices.

FIG. 11C represents the results of a two-dimensional solution of aPoisson equation.

FIG. 11D is a combined emission and optical reflection image of anavalanching test device.

FIGS. 12 and 13 illustrate a SiC junction-blocked Schottky-barrierrectifier (JBS).

FIG. 14 is a block diagram that illustrates a unit cell of across-sectional view of a shielded SiC metal-oxide-semiconductorfield-effect transistor (MOSFET) device.

DETAILED DESCRIPTION

FIG. 1 is a diagram that illustrates a side cross-sectional view of asilicon carbide high voltage high power device 100 (which can bereferred to as a SiC power device or as a SiC high voltage device) thatutilizes an ion-implanted junction termination extension (which can bereferred to as a junction termination extension (JTE) implant 140) in atermination region 102. The termination region 102 (which is toward theright in the figure) can be disposed around (e.g., can surround) anactive region 104 (which is toward the left (in a lateral direction) inthe figure). When viewed from the above (not shown), the terminationregion 102 can be disposed around an outer region of the SiC powerdevice 100 and can be disposed around (e.g., can surround) the activeregion 104, which can be disposed within an interior region of the SiCpower device 100.

To define the termination region 102, at least some acceptor charge atthe outer periphery of a semiconductor region 160 of the SiC powerdevice 100 is removed to define (e.g., expose) a surface 162. Thesurface 162 is vertically disposed at a depth within the semiconductorregion 160 that is lower than an interior portion (toward the left) ofthe semiconductor region 160 including the active region 104 (which isillustrated by the dashed line A (also can be referred to as plane A)).Specifically, at least some acceptor charge within the terminationregion 102 is partially removed by etching (e.g., an ion etch) of atopmost layer of the semiconductor region 160 (from the surfaceillustrated by the dashed line A). During processing, the surface 162 isan exposed surface of the semiconductor region 160 that has beenrecessed below line or plane A (which can be an original surface of thesemiconductor region 160 before being recessed). The surface 162 of thesemiconductor region 160 is within, or defines, a recessed region orrecessed area.

As shown in FIG. 1, the inner part of the termination region 102 (andthe surface 162 of the semiconductor region 160 that is exposed) iscoated with a dielectric layer 150 (or coating) having a portion 120with a low interface state density. In other words, the dielectric layer150 is disposed on the surface 162 of the semiconductor region 160. Thisportion can be referred to as a low interface state portion 120 (alsocan be referred to as a low interface state density portion or as a lowinterface state layer) or as a low interface state dielectric. In someimplementations, the low interface state portion 120 can be made of amaterial of gate oxide quality (e.g., can have the interface statedensity low enough to ensure the possibility of forming an inversionand/or accumulation channel). In some implementations, the low interfacestate portion 120 can include oxygen, nitrogen, and/or combinationsthereof (e.g., oxygen (O₂), an oxy-nitride, nitrogen oxide (NOx),nitrous oxide (N₂O)). In some implementations, the low interface stateportion 120 can include an oxide-nitride-oxide (ONO) stack.

As noted above, the low interface state portion 120 can be a portion ofthe dielectric layer 150. Although not labeled, portions of thedielectric layer 150 outside of the low interface state density portion120 can be referred to as a high interface state density portion.Accordingly, throughout the description, references to the dielectriclayer 150 can be considered as references to the high interface statedensity portion of the dielectric layer 150. An interface is defined bythe juxtaposition of the low interface state density portion 120 withthe dielectric layer 150. In some implementations, the low interfacestate density portion 120 can be separate from the dielectric layer 150.In some implementations, the low interface state density portion 120 canbe formed from the dielectric layer 150 or can be a dielectric layerformed separate from (e.g., during a separate dielectric formationprocess from) the dielectric layer 150.

As shown in FIG. 1, the low interface state portion 120 is in contactwith a top surface of the JTE implant 140. In some implementations, thelow interface state portion 120 has a bottom surface in contact with thesurface 162 (which can be a top surface) of the JTE implant 140. Inother words, the low interface state portion 120 defines an interfacewith the JTE implant 140.

In some implementations, the JTE implant 140 can be implanted before thesurface 162 of the semiconductor region 160 is defined. In someimplementations, the JTE implant 140 can be implanted after the surface162 of the semiconductor region 160 is defined.

In some implementations, the semiconductor region 160 can include asubstrate portion 164 (e.g., an N+ substrate) and a voltage blockinglayer 166 (e.g., an N-type voltage blocking layer),In someimplementations, the voltage blocking layer 166 can define, or caninclude, a drift region. The semiconductor region 160 can include adoped region 130 (e.g., a P+region) or well region. The doped region 130can be associated with, or included within, the active region 104. Insome implementations, the doped region 130 can have a dopingconcentration of between approximately 1e17 cm⁻³ and 1e19 cm⁻³. Thedoping concentration (e.g., peak doping concentration) of JTE implant140 can be between approximately 5e17 cm⁻³ and 2e18 cm⁻³. An edge of thedope region 130 can be aligned with (e.g., vertically aligned with) theactive region 104 and the termination region 102.

The doped region 130 can have a conductivity type different than aconductivity type of the blocking layer 166. The JTE implant 140 canhave a conductivity type that is the same as the conductivity type ofthe doped region 130. The substrate portion 164 can have a conductivitytype that is the same as a conductivity type of the blocking layer 166.

In some implementations, the active region 104 of the device 100 shownin FIG. 1 can be an epitaxial PN diode, which can be formed bydeposition of an epitaxial p-type layer 130 (which can be referred to asa mesa) with subsequent p-layer removal along the device periphery. Thetermination region 102 can, in some implementations, partially overlapthe active region 104 so as to avoid gaps between the active region 104and the termination region 102.

As shown in FIG. 1, the low interface state portion 120 has or includesa first portion aligned along or disposed on top of a surface (alongline or plane A) of the semiconductor region 160 and has or includes asecond portion disposed within the recessed region that is recessedbelow the semiconductor region 160. In other words, the second portionis disposed on the surface 162. In some implementations, the dielectriclayer 150 (or high interface state portion of the dielectric layer 150)is disposed on the low interface state portion 120 such that a firstportion of the low interface state portion 120 is disposed between thedielectric layer 150 (or high interface state portion of the dielectriclayer 150) and the doped region 130 and a second portion of the lowinterface state portion 120 is disposed between the dielectric layer 150and the JTE implant 140.

In some implementations, the low interface state portion 120 can bedisposed around an edge of a diode anode (or PN junction) defined by,for example, the doped region 130 and the voltage blocking layer 166.The diode anode (or PN junction) is illustrated at PN interface 132. Insome implementations, the low interface state portion 120 can be a lowinterface-state density oxide. In some implementations, the lowinterface state portion 120 can, for example, be a deposited oxide (ofthe dielectric layer 150 (e.g., a nitrided oxide) that is at leastpartially converted to an oxynitride by annealing in N₂O (e.g., or NO)ambient at, for example, 1100° C. to 1300° C. For example, the lowerinterface state portion 120 can include an oxide-nitride-oxide (ONO)stack. In some implementations, the low interface state portion 120 canbe a phosphorus doped oxide. In some implementations, the low interfacestate portion 120 can be, or can include, any combination of theabove-identified materials. Interface density reduction in SiC can alsobe employed. In some implementations the diode 100 can be peripheralportion (or in the termination region 102) of a MOSFET, of a NPN-typeBJT, and/or of a junction-blocked Schottky diode (JBS). In other words,an active device such as a MOSFET, a NPN-type BJT, a JBS, and/or soforth can be disposed in the active region 104. Examples of such devicesare described in connection with at least FIGS. 12 through 14.

In some implementations, the thickness of the low interface stateportion 120 can approximately between 10 nanometers (nm) to 200 nm. Insome implementations, the thickness of the low interface state portion120 can approximately between 20 nm to 50 nm. The thickness of thedielectric layer 150 (which can be a passivation dielectric) can beapproximately between 500 nm and 2000 nm (which can be relatively thickto isolate the semiconductor surface from the ambient). Accordingly, thethickness of the low interface state portion 120 can have a thicknessthat is be between 2.5 to 200 times less than the thickness of thedielectric layer 150.

In some implementations, a dose (e.g., a dose of a dopant or chargeconcentration) of the JTE implant 140 can vary laterally. A side orportion of the JTE implant 140 relatively close to the active region 104can be referred to as an active region side or portion 142 of the JTEimplant, and a side or portion of the JTE implant 140 further from theactive region 104 (toward the right) and disposed in the terminationregion 102 can be referred to as an termination region side or portion144 of the JTE implant. For example, a dose of the JTE implant 140 candecrease from left to right (from being highest on the active regionside to lowest on the termination region side). Accordingly, chargedensity can be removed from the termination region side of the JTEimplant 140 (relative to the active region side of the JTE implant 140).In some implementations, the JTE implant 140 can have a thickness (ordepth) on a side (the active region side or portion) adjacent the dopedregion 130 (closer to the active region 104) that is less than athickness of the remainder (the termination region side or portion) ofthe JTE implant 140 (laterally into the termination region 102). Inother words, the JTE implant 140 can have a depth below (or adjacent)the doped region 130 that is shallower than a depth of the remainder(the termination region side or portion) of the JTE implant 140(laterally into the termination region 102 and below the dielectriclayer 150 (and not below the doped region 130)). In someimplementations, the JTE implant 140 can be thinner (or shallower) (inthe active region side or portion) because the JTE implant can be formedthrough the doped region 130. The doped region 130 can have a bottomsurface in contact with a top surface of the JTE implant 140 such thatthe doped region 130 defines and interface with the JTE implant 140.

As shown in FIG. 1, cross-sections or cuts along the SiC power device100 have different stack profiles. For example, cut B1 has a profile ofdielectric layer 150, low interface state portion 120, doped region 130,voltage blocking layer 166, and substrate portion 164. Cut B2 has aprofile of dielectric layer 150, low interface state portion 120, dopedregion 130, JTE implant 140, voltage blocking layer 166, and substrateportion 164. Cut B3 has a profile of dielectric layer 150, low interfacestate portion 120, JTE implant 140, voltage blocking layer 166, andsubstrate portion 164. Cut B4 has a profile of dielectric layer 150, JTEimplant 140, voltage blocking layer 166, and substrate portion 164.

In some implementations, premature breakdown over a periphery of adevice (outside of the active region 104) can result in undesirableperformance of the power device 100. A uniform avalanche breakdown canbe achieved in the bulk (or active region 104) of the SiC power device100 using, for example, the termination region 102 configuration shownin FIG. 1. In other words, undesirable breakdown in the termination 102(before breakdown in the active region 104) can be avoided. Theconfiguration shown in FIG. 1 can have advantages over devices includingpositive angle beveling and low voltages.

FIG. 2 is a diagram that illustrates a variation of the sidecross-sectional view of the silicon carbide high voltage high powerdevice 100 shown in FIG. 1. At least some of the features shown in FIG.1 can be incorporated into FIG. 2.

As shown in FIG. 2, the termination region 102 includes a stair-likeprofile or multiple zones (in contrast to the single zone shown in FIG.1). A surface 163 of the semiconductor region 160 has a depth that islower than a depth of the surface 162. Accordingly, a thickness F1 ofthe JTE implant 140 associated with surface 162 (which can be referredto as a first zone) is greater than a thickness F2 of the JTE implant140 associated with surface 163 (which can be referred to as a secondzone). The first zone can be disposed between the active region 104 andthe second zone. In some implementations, a termination region can havemore than two zones (e.g., multi-zone). In some implementations, thetermination region 102 can include multiple zones each having (ordefining) a top surface at a different depth within the semiconductorregion 160.

As shown in FIG. 2, the JTE implant 140 has a first top surface portiondefining a first recess associated with the first zone and a second topsurface portion defining a second recess associated with the secondzone. The first top surface of the JTE implant 140 defines surface 162(which is a first recess below line or plane A) and the second topsurface portion of the JTE implant 140 (which is a second recess belowline or plane A). As shown in FIG. 2, the low interface state portion120 is disposed on the surface 162 (associated with the first zone) andnot disposed on the surface 163 (associated with the second zone). Insome implementations, the JTE implant 140 defines a top surface ofmultiple recesses (FIG. 2 illustrates such an example), the lowinterface state portion 120 can be in contact with at least one of themultiple recesses.

In some implementations, approximately 5-20% of the acceptor density ofthe entire JTE implant 140 can be removed in the second zone. In someimplementations, the thickness F2 of the JTE implant 140 can be 20% to70% less than the thickness F1 of the JTE implant 140.

In some implementations, the JTE implant 140 according to theembodiments described above may be capable of total or substantialsuppression of peripheral breakdown. In some implementations, uniform orsubstantially uniform bulk avalanche breakdown in the bulk of SiC(e.g.,active region) can be achieved. No spots or stripes of light emissionalong the device periphery due to peripheral avalanche breakdown areobserved. For high voltage (e.g., over 400 Volts) SiC devices havingnear-planar junction termination, uniform avalanche breakdown was notpossible without the termination configurations described above. In someimplementations, the termination region 102 can be configured to handle(e.g., sustain without failure) at least 50 milli-Joules (mJ) ofavalanche energy without failing (e.g., without peripheral breakdown).

In FIG. 3, an almost uniform avalanche breakdown is demonstrated byphoto micrograph light emission from a SiC PN diode at a voltage ofapproximately 1714 volts (V) at a current of approximately 1.5milli-amperes (mA). The bright area 301 illustrates uniform breakdownacross the termination region 302 on the right side of the device and anactive region 304 is on a left side of the device. In the implementationshown in FIG. 3, the SiC power device has a relatively large p-typeanode area (or power device area) of around 4 mm².

The termination (including the JTE implant 140) included in the SiCpower device 100 (shown in, for example, FIGS. 1 and 2) can providefavorable characteristics (e.g., relatively high energies) for, forexample, Unclamped Inductive Switching (UIS).

FIG. 4 is a graph that illustrates a sustained (e.g., a maximumsustained) UIS energy (or avalanche energy along the y-axis) as afunction of pulse duration or length (shown as time in microsecondsalong the x-axis). In other words, FIG. 4 illustrates single-pulseavalanche energy. Each of the pulses are shown as diamonds and a trendline through the data is illustrates as a straight line. The avalancheenergy was obtained by integration of dissipated power, i.e. of theproduct of avalanche current times the voltage over the time. Thecurrent traces were approximately triangular, i.e. the coil currentlinearly decreased with time after turn-off of the switch that was usedto control the energy stored in the induction coil. The three groups ofdata points having approximately the same pulse duration correspond tothe coil inductance L values of L=0.02 mH (for the shortest pulse around1.5 μs), L=0.5 mH (for the medium-duration pulse around 15 μs) and L=20mH (for the longest pulse around 150 μs) The avalanche breakdown voltagewas around 2 kV, whereas the peak avalanche current decreased fromaround 180 A for the shortest pulse (for L=0.02 mH) to around 8.5 A forthe L=20 mH. The UIS energy is approximately 2 times higher than, forexample, some known SiC devices (e.g., a 1200 V SiC junction-blockedSchottky (JBS) diode with Ea=200 mJ for inductance of 0.6 milli-Henries(mH) and 4 mm² anode area). In this example implementation, the diode(included in the SiC power device 100) can have an energy ofapproximately 500 to 600 mJ for 0.5 mH and a 4.76 mm² anode.

FIG. 5 is a graph that illustrates a distribution of breakdown voltages(on the y-axis) over an area of a SiC power BJT wafer (Vcbo) before (ina single zone such as that shown in FIG. 1) and after an etch (in asecond zone such as that shown in FIG. 2) into a periphery of anion-implanted JTE. The single zone test results are illustrated withsquares and the two zone test results are illustrated with upside-downtriangles. The before etch and after etch in this implementation eachinclude a low interface state portion (e.g., a low interface statedielectric). In some implementations, the etch can be on the order of ahundred nanometers in depth (e.g., 50 nm, 150 nm, 250 nm). In someimplementations, the implanted dose can be an aluminum (Al) dose ofapproximately 1.7×10¹³ cm⁻². In some implementations, the implant caninclude a different material (a different dopant) and/or can be adifferent concentration (higher or lower). In some implementations, thedevice chips (which have chip identifier numbers in FIG. 5 on thex-axis) included in the wafer can be probed sequentially in a serpentinepattern as shown on the schematic wafer image shown in FIG. 6. In thisimplementation, the etch increases voltage breakdown by over 60%. Thebreakdown voltage profiles of etched JTE mirror the U-shapeddistribution of donor in the low-doped collector over the wafer area. Insome devices, device termination techniques may be based on measurementsthat are done on very few or single selected components. This approachcan result in technologies that are not applicable to commercialmanufacturing or scaling. FIG. 5 illustrates that a small amount ofoperable high-voltage devices can be achieved. A few data points on thecurve marked as single zone in FIG. 5 are indeed acceptable from thestandpoint of blocking voltage, for which the target is approximately1200 Volt in the case for the data plotted in FIG. 5. However, the yieldof operable high voltage devices might in fact be very low, whichrequires improved junction termination techniques, such as thosedisclosed herein.

FIGS. 7A through 7D illustrate top view images of a test PN diode with amesh electrode. FIG. 7A-7D illustrates stages of development ofnear-uniform breakdown at currents of 0 mA (FIG. 7A), 10 mA (FIG. 7B),0.5 mA (FIG. 7C), and 0.005 mA (FIG. 7D).The reverse bias is 0 V (FIG.7A), 1772 V (FIG. 7B), 1770 V (FIG. 7C), and 1669 V (FIG. 7D). Thestreaky pattern in the images of FIGS. 7C and 7D can appear from fieldconcentration at material imperfections. As illustrated in FIGS. 7A-7D,peripheral breakdown does not occur at any stage of development ofavalanche breakdown (not even at 99.8% of the bulk breakdown voltage).In FIG. 7A, areas that are brighter with rounded edges in the image arethe regions 163 shown in FIG. 2 etched into SiC.

The SiC power devices described herein have greatly decreased area ofthe termination region as compared to the designs that are employed inknown devices. In some implementations, a breakdown voltage can changewith changes in a ratio between a width of a first zone (e.g., a lateralzone width) and a width of a second zone (e.g., a lateral zonewidth),Illustration of these zone widths (or length) are shown as firstzone S1 and second zone S2 in FIG. 2. The first zone S1 can be disposedbetween the active region 104 and the second zone S2. Both the firstzone S1 and the second zone S2 are disposed in the termination region102. Breakdown voltage characteristics based on zone width (orlength)are illustrated in, for example, FIG. 8.

As shown in the graph in FIG. 8, a first zone is labeled S1 and a secondzone can be referenced as S2. The graph in FIG. 8 illustrates blockingvoltage along the x-axis and current in mA along the y-axis. As shown inFIG. 8, a 1.5% decrease of a blocking voltage (which can be referred toas a breakdown voltage) occurs with a decrease of the JTE width for eachof the zones from 55 microns to 10 microns. In FIG. 8, the width of zoneS2 is equal to the width of zone S1. In some implementations, the widthof zone S1 can be different than (e.g., longer than, shorter than) thewidth of zone S2. Narrowing of the junction termination width results inimproved utilization of the chip area, which may be desirable in, forexample, commercial manufacturing.

FIG. 9 is a diagram that illustrates formation of a high voltagetermination within a SiC power device 900 in accordance with theimplementations described herein. The implementation shown in FIG. 9 isderived at least from the implementations shown in FIGS. 1 and 2.

In this implementation, a high voltage termination in a terminationregion 902 is formed by ion implantation of acceptor ions into an n-typevoltage blocking layer 966 (e.g., a low-doped n-type voltage blockinglayer), which is above a substrate 964 (e.g., n-type substrate). In someimplementations, acceptor ions can be activated by a high temperatureanneal between, for example, approximately 1500° C. and 1800° C. In someimplementations, the dose of the electrically active acceptors of theimplant can slightly exceed the characteristic acceptor dose, Q_(aval),Q_(aval)=εεE_(aval)/q , where E_(aval) is the peak electric field atavalanche breakdown, ε the relative permittivity of SiC, ε₀ is thevacuum permittivity, and q is the electron charge. Using theseprocesses, a JTE implant 940 is defined within the termination region902. An active region 904 is also indicated in FIG. 9.

In some implementations, an outer region of a JTE termination can bethinned down by an etch (e.g., a reactive ion etch, a plasma etch),which is illustrated with vertical arrows, so as to decrease theelectrically active acceptor dose to a number, which is slightly belowQ_(aval). In some implementations, the lateral extensions of each JTEzone W1 and W2 can exceed approximately ½ (or more or less) of a driftregion thickness WD. Although not illustrated, after the etch, a lowinterface state portion (e.g., low interface state portion 120) and adielectric layer (e.g., dielectric layer 150) can be included in (e.g.,disposed on) the SiC power device 900.

In some implementations, an electric field at the JTE termination of aSiC PN diode (at PN interface 932), can have advantages in a two-zonetermination over a single-zone termination. For a low acceptor dose,strong concentration of electric field can occur at the edge of thediode anode. A higher dose can result in a relatively strong fieldconcentration around an outer edge of the JTE implant. In someimplementations, the boundary of the JTE to the active region can bereferred to as the inner edge of the JTE, whereas the other edge of theJTE implant can be referred to as the outer edge of the JTE. In someimplementations, a two-zone termination can suppress the electric fieldconcentration.

As noted above, the configurations described herein can result in anincrease of breakdown voltage in the termination region 902 over otherdesigns. In some implementations, in the configurations describedherein, the hot carriers due to breakdown may be trapped into adielectric at the SiC surface. The charge due to carrier trapping canresult in an increase in the breakdown voltage.

FIG. 10A is a diagram that illustrates one possible theory associatedwith the SiC power devices described herein. In some implementations,hot carrier capturing may not be identical for two types of insulators:much lower capturing may be expected for the low interface state portion1020 (e.g., low interface state dielectric) than the high interfacestate portion 1050. The hot carrier path is illustrated as arrow 10 andcharge trapping locations are represented by circles with plus signs.This difference in capturing can provide a step in sheet electric chargeof the JTE implant 1040. Such a JTE charge profile can be desirable fora minimization of electric field spikes. The capturing process may bealso self-controlled, at least within a certain range of implantedacceptor dose (e.g., implanted Al acceptor dose).

In some implementations, SiC can be more susceptible to failure at thespots of localized breakdown than silicon (Si), because of, for example,the dynamic resistance of an avalanching junction is inverselyproportion to the square of the breakdown field. For SiC, this canresult in a factor of one-hundred (100) difference compared withsilicon. The reliability of SiC power devices can be significantlyimproved by suppressing early avalanche breakdown at the periphery ofthe SiC power devices. In some implementations, a termination of a SiCpower device can have at a least zone etched into an ion implanted JTEwith a breakdown voltage over 95% of the bulk value. This possibility isnot obvious in view of the fact that simulations predict much strongerconcentration of electric field by the periphery.

FIG. 10B is a graph that illustrates a capacitance-voltagecharacteristic of a metal-oxide-semiconductor (MOS) structure, which isformed using the low interface state portion (e.g., low interface statedensity dielectric (e.g., a low interface state density oxide)).The MOScapacitance (C) is illustrated along the y-axis and gate voltage (Vg) isillustrated along the x-axis. As mentioned above, such low interfacestate portions can be, for example, formed by depositing an oxide ontoSiC with subsequent high-temperature anneal in N₂O-containing ambient.The MOS capacitor, in this implementation, has a diameter ofapproximately 0.1 millimeter (mm). The capacitance-voltagecharacteristic shows a clear accumulation region at a positive gate biasand a region of deep depletion at a negative gate bias, which indicatesa low density of interface traps. This high quality interface is, inthis case, formed by passivation of dangling bonds in the near-interfacelayer of silicon oxynitride, which layer can be a result of annealingthe silicon dioxide layer on SiC in presence of N₂O. In contrast,as-deposited chemical-vapor deposited (CVD) or plasma-enhanced CVD(PECVD) silicon dioxide may have a high density of interface traps, andmay not show as pronounced accumulation region as that shown in FIG.10B. Other techniques can be also applied for formation of low interfacetrap density dielectrics on SiC. As an example, the layer of silicondioxide can be formed by thermal oxidation rather than by deposition. Insome implementations, hydrogen passivation of interface traps may beused instead of nitrogen passivation through annealing the interface inwet oxygen. In some implementations, hydrogen passivation can be alsocombined with nitrogen passivation.

FIGS. 11A and 11B illustrate schematic cross-sections of an edge of anion-implanted PN diode with a JTE (similar to those described and shownabove). FIG. 11B shows a cross-section of the device 1100 shown in FIG.11A after partial removal of the ion-implanted JTE implant 1140 from theouter portion of the JTE implant 1140 to define a two-zone device. Inother words, FIG. 11A illustrates a single-zone device and FIG. 11Billustrates a two-zone device. Both devices 1100 are illustrated withouta low interface state portion or dielectric layer. A doped region 1130,a substrate 1164, an active region 1104, and a termination region 1102are illustrated.

FIG. 11C shows the lateral profile of electric field in the vicinity ofthe crystal surface, which is simulated using two-dimensional technologysoftware by solving the Poisson Equation. FIG. 11C illustrates theelectric fields for devices similar to those shown in FIGS. 11A and 11B.The blocking layer (e.g., block layer 1166) thickness in this simulationis approximately 10 μm (although the thickness is presented by way ofexample only). The JTE implant length of a single-zone (1-zone) JTEimplant is approximately 10 μm (e.g., point N1 to N2 in FIG. 11A), atwo-zone (2-zone) JTE has a length of approximately 10 μm in both thefirst (inner) JTE zone (e.g., point M1 to M2 shown in FIG. 11B) and forthe second (outer) JTE zone (portion M2 to M3 shown in FIG. 11B).

The profile of electric field for the single-zone JTE shows two peaks atthe anode edge (in the vicinity of x=0 (i.e., N1 in FIG. 11A)) and atthe outer edge of the JTE, at approximately x=10 (i.e., N2 in FIG. 11A).The relative height of these peaks depends on JTE dose (i.e., 1.5e13cm⁻² or 1.0e13 cm⁻²), however both of them are present in the profiles(including the two-zone profile). In some implementations, depending onthe acceptor dose in the JTE, the avalanche breakdown can occur eitherat the inner edge of the JTE (at x=0), or at the outer edge of the JTE(at x=10) or at both locations.

An image of emission due to highly localized avalanche breakdown at theouter JTE edge of a test structure is shown in FIG. 11D. The teststructure imaged in FIG. 11D is lacking any etched second JTE zone andcorresponds to the cross-section schematically shown in FIG. 11A. A highvoltage of around 1200 Volt was applied to the device. The emissionoccurs due the avalanche current of around 0.1 mA and is seen in FIG.11D as portions of a bright vertical line to the left from the anodecontact. The emission is superimposed on reflected-light image byilluminating the diode wafer with the prober microscope lamp. The imagedistortion is due to the dielectric liquid used for prevention ofair-gap sparks. Further increase of the reverse current in thiscomponent results in component destruction due to high density of powerdissipation. This happens at an avalanche current of a few mA, even inthe pulsed mode of operation. With highly localized breakdown as in thiscase, it may not be (or is not) possible to achieve a total avalanchecurrent between approximately 10 A and 200 A (which are currentspresented by example).

Referring back to FIG. 11C, it is further demonstrated by solution ofthe Poisson Equation for the two-zone (or multi-zone) JTE, that themultiple-zone design may not (or does not) eliminate the additionalpeaks of the electric field at the edge of the adjacent JTE zones. Suchadditional peaks are visible at the anode edge (in the vicinity of x=0(i.e., M1 in FIG. 11B)), at approximately x=10 (i.e., M2 in FIG. 11B),and at the outer edge of the JTE, at approximately x=20 (i.e., M3 inFIG. 11B) for the simulation of the two-zone termination plotted in FIG.11C. In some implementations, it may not (or is not) possible to keepthe electric field in all (or many) locations of the JTE region (i.e. atlocations N1, N2, M1, M2, and M3) and/or stay below the electric fieldin the anode region, i.e. at x>0. Peaks M1 and M3 (shown in FIG. 11C)will appear due to electric field concentration at inner and outer edgeof the JTE respectively. Peak M2 (shown in FIG. 11C) will appear in atwo-zone JTE at the interface of the two JTE zones that have differentacceptor charge. Such peaks of electric field cause localized earlybreakdown and these locations may have an avalanche breakdown at anearlier voltage than the anode. Highly localized early breakdown canpotentially result in device failure at a low avalanche current underthe conditions of UIS.

The implementations according to this description have favorableavalanche robustness as compared to what is expected from solutions ofthe Poisson equation. The avalanche current tolerated by devicesaccording to these implementations is high, approximately 10 A to 200 Aat a reverse bias of around 2 kV, as is demonstrated in, for example,FIG. 4. Further on, emission images shown in FIG. 7 do not show regionsof early breakdown in expected weak spots, such as locations M1, M2, orM3. There exists a contradiction between the results of the PoissonEquation solution, which are unexpected due to the fundamental nature ofthe Poisson Equation.

The model presented within discussion of FIG. 10 provides one possibleexplanation of the results presented in this disclosure. In someimplementations, interface trapping of mobile carriers may affect thecharge balance under the conditions of avalanche breakdown. The trappedcarriers may smooth the peaks of electric field in locations M1, M2 andM3. In some implementations, other phenomena, other than the interfacecharge trapping, may be involved. In some implementations, carrier trapsmay also originate from residual damage due to ion implantation in SiCor even from the dry etching procedure that is used for partial materialremoval in the JTE region. Further on, the charge trapping phenomenamight be dynamic rather than static. These trapping phenomena thatresult in better-than-theoretical performance are disclosed by exampleonly and may not be the only mechanisms.

The termination regions and structures including a JTE implant (asdescribed above) may be used in connection with any of the activedevices described below in connection with FIGS. 12 through 14. Theseactive devices can be included in, for example, an active region.

FIG. 12 represents a unit cell 531 of a Schottky-barrier dioderectifier. The unit cell 531 of the rectifier can be formed on anoff-oriented heavily doped n-type 4H SiC substrate 550. A lightly dopedn-type epitaxial drift region 540 having a thickness DR0 is disposed onthe substrate 550. An optional buffer layer 541 is disposed betweensubstrate 550 and drift region 540 to, for example, mitigate substratecrystal imperfections. The doping (e.g., doping concentration or dopinglevel)of the buffer layer 541 can be at least several times higher thanthe doping of the drift region 540 in some implementations, however itcould approach the n-type doping of the substrate 550. The unit cell 531can include a trench 533 having a trench bottom 532 (or bottom surface)and trench sidewalls 533A and 533B. A heavily doped ion-implanted p-typeregion 534 can be included adjacent the trench sidewalls 533A, 533B andtrench bottom 532. A heavy acceptor doping exceeding 10²⁰ cm⁻³ can beincluded in the region 531, at least near the trench bottom 532 and/orthe surface of trench walls 533A and 533B. A portion 535 of the SiC mesasurface can have an n-type conductivity. A metal contact 536 can beincluded on top of the semiconductor region 560 so as to form a Schottkybarrier to n-type portions of SiC the portion 535. An Ohmic contact withcontact 551 can be included at the back side of the crystal. Implantedregions of neighbor unit cells (similar to unit cell 531) can form aperiodic PN diode grid, which can be oriented (or shaped) in anelongated fashion along an off-orientation direction OD as describedherein.

One advantage of using a PN diode grid in a Schottky-barrier rectifieris electrostatic shielding of shielding of the Schottky-barrier metal,which could be otherwise exposed to, for example, a high electric field.Avalanche breakdown in a junction barrier Schottky (JBS) diode can occurat the PN-diode grid, which can resolve reliability issues that canarise in a non-shielded Schottky-barrier rectifier. The trench design ofthe JBS can be more readily design optimized as compared to a fullyplanar design, because the depth of the p-body can be readily increasedto a specified value without using, for example, high implant energies(which may not be practical in manufacturing).

Another advantage of the PN diode grid is its handling of a high forwardsurge current. A Schottky-barrier rectifier without a built-in PN bodydiode may not be as robust in handling an overload in on-state current,because device self-heating results in a drop in carrier mobility and inincrease of the forward voltage drop as result. In contrast, the PNdiode grid of a JBS rectifier can have a behavior, which is similar tothe behavior of a planar PN diode. A high forward bias in a PN-diode canresult in injection of minority carriers, which can minimize the forwardvoltage drop and permit relatively fail-safe operation under theconditions of forward-current overload. Though beneficial, suchinjection represents a reliability risk due to the bipolar degradationvia growth of stripe-type stacking faults. According to this embodiment,such risk is mitigated by sectioning the rectifier in elongatedsub-components as described herein.

The high power rectifier is sectioned in two or more elongatedsub-component rectifiers of smaller area, each sub-component having thelonger side that is parallel to the off-orientation direction. Eachsub-component can include an array of unit cells 531. A cross-section ofthe region between sub-component rectifiers according to this embodimentis shown in, for example, FIG. 13.

A sub-component rectifier can include a continuous rim of anode implant537 as shown in FIG. 13. In FIG. 13 such rims are shown as 537A and 537Bfor two neighbor sub-components. Field-limiting regions 521A, 521B, and521C are disposed between the adjacent rectifiers to avoid or minimizeelectric field concentration. Regions 521A, 521B, and 521C are providedmedium-dose acceptor implant. The role of the field-limiting regions canbe same as that of a Junction Termination Extension at the deviceperiphery as described herein. The requirements to optimum implant dosein these regions can be the same as those known for design of the JTE.The optimum dose of electrically active acceptors can be slightly(approximately 5% to 20%) lower, that the characteristic dose Q_(A),which dose Q_(A) corresponds to full depletion of such p-type region atthe conditions of avalanche breakdown. The characteristic dose Q_(A) isgoverned by the Gauss Law, Q_(A)=E_(CR)ε₀ε_(R)/q, where E_(CR) is thecritical field for avalanche breakdown, ε₀ the vacuum permittivity ε_(R)the relative permittivity of SiC and q the electron charge. Gaps 522Aand 522B in p-implant can be formed between regions 521A and 521B, aswell as between 521B and 521C. The gaps 522A and 522B can be formed witha relatively narrow width that can be substantially smaller than thethickness of the drift region DR0. Forming the gaps 522A, 522B in thefield-limiting implant substantially narrow will prevent excessiveconcentration of electric field next to the gaps 522A, 522B. The gaps522A, 522B can prevent (or substantially prevent) lateral current flowunder the conditions of a high forward bias and it will therefore assisttermination of stacking fault (SF) propagation. The number of gaps 522A,522B in the field-limiting implant can optionally be greater than 2 soas to further assist suppression of SF propagation. The SiC surface inthe region between neighbor subcomponents can further include adielectric coating 523.

FIG. 14 is a block diagram that illustrates a unit cell 600 of across-sectional view of a shielded SiC metal-oxide-semiconductorfield-effect transistor (MOSFET) device (also can be referred to as avertical MOSFET device). As shown in FIG. 14 an epitaxial layer 660(e.g., N-type) is disposed over a substrate 662 (e.g., N+ substrate). Asource region 666 (e.g., N+ source region) and a body region 664 (e.g.,p-type body region) are formed. A heavily doped p-type subcontact region665 is formed in the body region 664 to, for example, minimizeresistance of the contact to the body region 664. A shallow donorimplant region 667 that can have dose between approximately 10¹² and5×10¹² cm⁻² is further included for, for example, control of a desiredMOSFET threshold voltage. The MOSFET can be normally in an off-state,and can include a gate dielectric 630. Gate 640 can overlap the topsurface including a portion of the source region 666 a portion of thebody region 664 and a surface of the lightly doped n-type SiC. A sourcecontact 671 can be applied to a well in the gate dielectric 630, whichcontact can also define an Ohmic contact to the body region 664 via thesubcontact region 665. A drain 672 contact can be included on a backside of the substrate. Source and drain contacts 671 and 672,respectively, can be formed by sintering nickel (Ni) to SiC so as todefine a nickel silicide. In some embodiments, the gate dielectric 630is a silicon dioxide with a layer of silicon oxynitride adjacent to adielectric interface to the SiC. Such a near-interface oxynitride layercan be formed by a high-temperature anneal of silicon dioxide dielectricon SiC in an ambient containing N₂O or NO.

The unit cell 600 shown in FIG. 14 can be duplicated in a large array todefine a MOSFET (also can be referred to as a MOSFET array). The unitcell 600 may be included in a 1-dimensional linear array or may bearranged as a 2-dimensional array in, for example, a rectangular or in ahexagonal pattern. The array can include 2-level metallization usinginterconnect techniques, which can be utilized in silicon power MOSFETtechnology. The MOSFET in an array according to this embodiment shouldbe substantially elongated along the direction of off-orientationdirection OD, in a similar manner to, for example, that disclosed forSiC rectifiers herein. The MOSFET can alternately sectioned in elongatedsub-components in the manner similar to that described herein.

In some implementations, a body diode of the unit cell 600 of the MOSFETcan be used as a rectifier, for example, in an inverter circuit. Theinjection of minority carriers may provoke growth of, for example,stripe-shaped stacking faults. The elongated shape of MOSFET array (orof sub-component a MOSFET array) can mitigate the degradation due to thegrowth of stacking faults.

Although the behavior of the circuits shown and described in the graphsherein as making transitions at specified voltages and at specifiedtimes, when implemented, the transitions of components may occurslightly before or slightly after the specified voltages, specifiedtimes, and/or so forth. Specifically, variations in threshold voltages,processing variations, temperature variations, switching speeds ofdevices, circuit transition delays, and/or so forth can result inconditions (e.g., non-ideal conditions) that can trigger transitions ofcomponents slightly before or slightly after the specified voltages,times, and/or so forth.

It will also be understood that when an element, such as a layer, aregion, or a substrate, is referred to as being on, connected to,electrically connected to, coupled to, or electrically coupled toanother element, it may be directly on, connected or coupled to theother element, or one or more intervening elements may be present. Incontrast, when an element is referred to as being directly on, directlyconnected to or directly coupled to another element or layer, there areno intervening elements or layers present. Although the terms directlyon, directly connected to, or directly coupled to may not be usedthroughout the detailed description, elements that are shown as beingdirectly on, directly connected or directly coupled can be referred toas such. The claims of the application may be amended to reciteexemplary relationships described in the specification or shown in thefigures.

As used in this specification, a singular form may, unless definitelyindicating a particular case in terms of the context, include a pluralform. Spatially relative terms (e.g., over, above, upper, under,beneath, below, lower, and so forth) are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. In some implementations, therelative terms above and below can, respectively, include verticallyabove and vertically below. In some implementations, the term adjacentcan include laterally adjacent to or horizontally adjacent to.

Implementations of the various techniques described herein may beimplemented in digital electronic circuitry, or in computer hardware,firmware, software, or in combinations of them. Portions of methods alsomay be performed by, and an apparatus may be implemented as, specialpurpose logic circuitry, e.g., an FPGA (field programmable gate array)or an ASIC (application-specific integrated circuit).

Implementations may be implemented in a computing system that includes aback-end component, e.g., as a data server, or that includes amiddleware component, e.g., an application server, or that includes afront-end component, e.g., a client computer having a graphical userinterface or a Web browser through which a user can interact with animplementation, or any combination of such back-end, middleware, orfront-end components. Components may be interconnected by any form ormedium of digital data communication, e.g., a communication network.Examples of communication networks include a local area network (LAN)and a wide area network (WAN), e.g., the Internet.

Some implementations may be implemented using various semiconductorprocessing and/or packaging techniques. Some implementations may beimplemented using various types of semiconductor processing techniquesassociated with semiconductor substrates including, but not limited to,for example, Silicon (Si), Galium Arsenide (GaAs), Silicon Carbide(SiC), and/or so forth.

While certain features of the described implementations have beenillustrated as described herein, many modifications, substitutions,changes and equivalents will now occur to those skilled in the art. Itis, therefore, to be understood that the appended claims are intended tocover all such modifications and changes as fall within the scope of theimplementations. It should be understood that they have been presentedby way of example only, not limitation, and various changes in form anddetails may be made. Any portion of the apparatus and/or methodsdescribed herein may be combined in any combination, except mutuallyexclusive combinations. The implementations described herein can includevarious combinations and/or sub-combinations of the functions,components and/or features of the different implementations described.

What is claimed is:
 1. An apparatus, comprising: a semiconductor regionincluding a silicon carbide material; a junction termination extension(JTE) implant region disposed in the semiconductor region; and a lowinterface state density portion of a dielectric layer having at least aportion in contact with the JTE implant region.
 2. The apparatus ofclaim 1, further comprising: a drift region having a first conductivitytype; and a doped region having a second conductivity type, the dopedregion being different from the JTE implant region, the JTE implantregion having the second conductivity type.
 3. The apparatus of claim 1,wherein the low interface state density portion includes a first portionaligned along a top surface of the semiconductor region and a secondportion disposed within a recessed region that is recessed below the topsurface of the semiconductor region.
 4. The apparatus of claim 1,further comprising: a doped region having a bottom surface in contactwith a top surface of the JTE implant region, the low interface statedensity portion being in contact with a top surface of the doped regionand in contact with a top surface of the JTE implant region.
 5. Theapparatus of claim 1, further comprising: a high interface state densityportion of the dielectric layer disposed on the low interface statedensity portion such that a first portion of the low interface statedensity portion is disposed between the high interface state densityportion of the dielectric layer and a doped region and a second portionof the low interface state density portion is disposed between the highinterface state density portion of the dielectric layer and the JTEimplant region.
 6. The apparatus of claim 1, wherein the low interfacestate density portion includes a low interface-state density oxide. 7.The apparatus of claim 1, wherein the low interface state densityportion is a deposited oxide of the dielectric layer at least partiallyconverted to an oxynitride.
 8. The apparatus of claim 1, wherein the lowinterface state density portion includes a phosphorus doped oxide. 9.The apparatus of claim 1, wherein the JTE implant region has a firstportion with a depth below a doped region less than a depth of a secondportion not below doped region.
 10. The apparatus of claim 1, whereinthe JTE implant region has a first top surface portion defining a firstrecess and a second top surface portion defining a second recess. 11.The apparatus of claim 1, wherein the JTE implant region defines a topsurface of a plurality of recesses, the portion of the low interfacestate density portion is in contact with at least one of the pluralityof recesses.
 12. The apparatus of claim 1, wherein the JTE implantregion is disposed in a termination region, the apparatus furthercomprising: an active region including an active device.
 13. Theapparatus of claim 1, wherein the JTE implant region and the lowinterface state density portion being included in a termination region,the termination region configured to handle at least 50 milli-Joules ofavalanche energy without failing.
 14. A semiconductor device,comprising: a semiconductor region including a silicon carbide material;a JTE implant region disposed in a termination region of thesemiconductor region; a doped region having a least a portion disposedover the JTE implant region; and a low interface state density portionof a dielectric layer disposed over at least a portion of the dopingregion and over at least a portion of the JTE implant region.
 15. Thesemiconductor device of claim 14, wherein the at least the portion ofthe JTE implant region is in contact with the low interface statedensity portion within a region recessed below a top surface of thesemiconductor region.
 16. The semiconductor device of claim 14, whereinthe doped region having a bottom surface in contact with a top surfaceof the JTE implant region.
 17. The semiconductor device of claim 14,further comprising: a high interface state density portion dielectriclayer disposed on the low interface state density portion such that afirst portion of the low interface state density portion is disposedbetween the high interface state density portion and the doped regionand a second portion of the low interface state density portion isdisposed between the high interface state density portion and the JTEimplant region.
 18. The semiconductor device of claim 14, wherein thelow interface state density portion includes at least one of a lowinterface-state density oxide, an oxynitride, or a phosphorus dopedoxide.
 19. The semiconductor device of claim 14, wherein the terminationregion includes a plurality of zones each defining a top surface at adifferent depth within the semiconductor device.